Sense and refresh circuits have long been known in the art. Optimization of the circuits for operation has been disclosed in "Optimization of the Latching Pulse for Dynamic Flip Flop Sensors" by W. T. Lynch and H. J. Boll, lEEE Journal of Sold State Circuits; Vol. SC-9 and "Storage Array and Sense/Refresh Circuit for Single Transistor Memory Cells" by K. U. Stein, A. Sihling and E. Doering, lEEE JSSC, Vol. SC-7, Oct. '72.
However, sense and refresh circuits have long suffered from excessive power consumption and design constraints. Thus there is a need for a sense and refresh circuit having low power consumption and improved design for use in high density integrated circuits.